The increasing complexity of electronic systems have led not only to the use of semiconductor chips with increasing scale of integration, but also of chip carriers with smaller bond pad geometries, closer bond pad pitches and higher net counts. Furthermore, as electronic circuits become faster and signal timings become more crucial, less tolerances are now affordable for deviations in electrical properties, such as resistance, inductance and capacitance, of carriers. As a result, it has become increasingly more difficult to attain high yield in the production of both chips and chip carriers. Compounding the problem is the growing cost of rework that is caused by the increasing scale of integration and the common use of multi-chip carriers.
For the above stated reasons, it has become economically important in the manufacturing of semiconductor devices not only to test the chips, but also the chip carriers prior to assembling them together to form a device.
However, as semiconductor devices operate faster and propagation speed of signals through the carriers becomes more crucial, prior art instruments that merely test for continuity of signal paths are no longer deemed satisfactory.
What is needed for increasing the yield of manufacturing semiconductor devices is a test technique and apparatus that can simulate the operating environment of the carriers.